Method of generating layout of semiconductor integrated circuit

Details Method of generating layout of semiconductor integrated circuit Method of generating layout of semiconductor integrated circuit

1996-10-30

1999-03-30

Teska, Kevin J.

Boots, shoes, and leggings

364489, G06F 1750

Patent

active

058896813

ABSTRACT:
A method of generating a hierarchical layout of cells of a semiconductor integrated circuit includes the steps of arranging an abstract cell in a target cell, setting the positions of second terminals in the abstract cell as compaction constraints on first terminals of the target cell, forming jogged lines, moving the first terminals having the compaction constraints to intersections between the jogged lines and an edge of the abstract cell, and compacting the target cell.

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