Manufacturing method and system for dynamic dispatching of integ

Boots – shoes – and leggings

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36446801, 36446805, 36446807, 36446809, 36446828, H03M 501

Patent

active

058896732

ABSTRACT:
In dynamic dispatching of integrated circuit wafer lots in an integrated circuit fabrication plant, determine the Stage Achievement Rate (SAR) of descendant stages for each candidate stage to be processed by the fabrication plant. With the loading of descendant stages for each candidate stage, determine the Adjusted Loading (AL), where AL=SAR*(Loading of descendant stages for each candidate stage). Determine the Picked Probability (PP) equal to Normalized 1/AL of grouped descendant stages. Determine the Estimated Loading (EL) of descendant stages for each candidate stage. Determine the Estimated Achievement Rate (EAR) of descendant stages for each candidate stage. Next, determine the Estimated Adjusted Loading (EAL) of descendant stages for each candidate stage. Then determine the Total Estimated Adjusted Loading (TEAL) for each candidate stage. Finally, determine the Dynamic Dispatching Order (DDO) of the wafer lots.

REFERENCES:
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patent: 5077661 (1991-12-01), Jain et al.
patent: 5128860 (1992-07-01), Chapman
patent: 5255181 (1993-10-01), Chapman et al.
patent: 5612886 (1997-03-01), Weng

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