Fishing – trapping – and vermin destroying
Patent
1986-02-27
1987-12-15
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437193, 437231, 437192, H01L 21441
Patent
active
047133562
ABSTRACT:
A method of manufacturing a semiconductor device wherein the proportion of the area occupied by the source and drain regions can be reduced. In this method, the side walls of a gate electrode are first selectively deposited with an insulating film, then conductive material layers are selectively formed on the source and drain regions, partially extending to side portions of an element isolation regions, and, after forming an insulating protective film over the entire surface of the resultant structure, contact holes are formed to reach the conductive material layers for forming source and drain wiring layers.
REFERENCES:
patent: 4274909 (1981-06-01), Venkataraman et al.
patent: 4462149 (1984-07-01), Schwabe
patent: 4512073 (1985-04-01), Hsu
patent: 4616401 (1986-10-01), Takeuchi
Gargini et al., "WOS: Low-Resistance Self-Aligned Source, Drain and Gate Transistors", Technical Digest of IEDM, pp. 54-57, (1981).
Moriya et al., "Encroachment-Free Tungsten CVD Process for Self-Aligned Source-Drain-Gate Mettalization", Digest of Technical Papers of Symposium on VLSI Technology, No. 83, (1983).
Chaudhuri Olik
Kabushiki Kaisha Toshiba
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