Method and apparatus for dynamically adjusting the number of sta

Details Method and apparatus for dynamically adjusting the number of sta Method and apparatus for dynamically adjusting the number of sta

1997-05-12

1998-07-07

Harrell, Robert B.

G06F 900

Patent

active

057782504

ABSTRACT:
A dynamic pipeline for a processor, including multiple latch stages for providing data to corresponding operation elements and multiplexers with associated control logic for bypassing one or more latch stages and operation elements to execute simpler instructions. For a graphics processor, multiplexers select input pixel values and alpha blending values from either internal or external sources. The pixel values are processed through an arithmetic and logic unit for performing logic operations with other pixel values or with offset scaler values. The alpha values are inverted for performing alpha blending functions. The pixel and alpha values are then provided to a first set of latches for providing latched data to the inputs of a multiplier. The output of the multiplier and another offset scalar value are provided to a second set of latches for providing latched data to an arithmetic element. The outputs of both the arithmetic element and the multiplier are provided to a third set of latches for providing latched data to another arithmetic element. Preferably, the third set of latches and the second arithmetic element may be implemented by the second set of latches and the first arithmetic element to save logic. A first multiplexer is provided to bypass the third set of latches and the second arithmetic element. A second multiplexer is provided to bypass the first set of latches and the multiplier. Control logic provides the signals to control the multiplexers to use the appropriate number of stages depending upon the instruction to be performed.

REFERENCES:
patent: 4996661 (1991-02-01), Cox et al.
Harold S. Stone "High-Performance Computer Architecture" (IBM ISBN 0-201-526883-3) (1993) pp. 142-450.

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