Ring bus multiprocessor system and processor boards for constitu

Details Ring bus multiprocessor system and processor boards for constitu Ring bus multiprocessor system and processor boards for constitu

1996-06-10

1998-07-07

Harvey, Jack B.

395281, 395311, 39520081, 395800, G06F 1300, G06F 1338

Patent

active

057782024

ABSTRACT:
A ring bus multiprocessor system whose processors are laid out and connected in such a manner that the system is enhanced in stability and performance, is easy to modify in scale, and is lowered in manufacturing cost. On a processor board, processors are serially connected by communication buses to form a processor group. Each processor board may have an even-numbered plurality of processor groups mounted thereon. A plurality of processor boards are laid out in parallel and are interconnected between adjacent boards by means of inter-processor communication buses. Each of the odd-numbered processor groups is connected from one board to the next up to the most downstream board where the connection is looped back to the adjacent even-numbered processor group. In turn, the even-numbered processor group is connected from one board to the next back to the most upstream board where the connection is again looped back to the adjacent odd-numbered processor group, and so on, whereby a ring bus arrangement is formed.

REFERENCES:
patent: 4667287 (1987-05-01), Allen et al.
patent: 5113525 (1992-05-01), Colley et al.
patent: 5359714 (1994-10-01), Avaneas
patent: 5488705 (1996-01-01), LaBarbera
Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE, VLD 93-99, ICD 93-194, (1993-03), "Topdown Design of a Monte Carlo Device Simulation Processor with Hardware Description Language", Norihiko Kuroishi et al., 8 pages. Abstract--Only part W/ English Translation.

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