Patent
1995-11-21
1998-07-07
Harvey, Jack B.
395296, 395729, G06F 1336
Patent
active
057782008
ABSTRACT:
A computer system for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of counters referred to as "aging factor" counters is further provided wherein a separate counter unit corresponds to each bus master. Each counter is configured to generate a signal indicative of a lapse of time since a time when the peripheral was last granted ownership of the bus. An arbitration control unit is coupled to the aging factor counters, the request detection unit and the grant generator for processing incoming bus request signals. The arbitration control unit is configured to dynamically vary the level of arbitration priority given to each peripheral device based upon the aging signal corresponding to the device. Accordingly, as a greater period of time elapses when a peripheral device last owned the bus, the greater the level of arbitration priority that is given to a bus request by that peripheral. A set of programmable registers are provided to allow software programming of the initial count value associated with each aging counter. The aging counter for a particular device may further be held or inhibited from counting to provide a constant level of priority for that particular peripheral device.
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Advanced Micro Devices , Inc.
Harvey Jack B.
Kivlin B. Noel
Pancholi Jigar
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