Multiphase series-parallel-series charge-coupled device register

Communications: electrical – Digital comparator systems

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340173CA, G11C 1140

Patent

active

040074463

ABSTRACT:
The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two-phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit. The input and output sections each contain the same number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site. Data bits are transferred from the input section to the central section in two phases. Data bits are also transferred from the central section to the output section in two phases. This interleaved mode of inter-sectional data transfer allows for input and output sections of a minimum size (in terms of number of cell sites required) and hence, a greater density CCD register. The interleaved mode also reduces the number of charge transfer from input to output, thereby providing inherent charge transfer efficiency.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 3797002 (1974-03-01), Brown
patent: 3913077 (1975-10-01), Erb

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