Multi-processor system for invalidating hierarchical cache

Details Multi-processor system for invalidating hierarchical cache Multi-processor system for invalidating hierarchical cache

1992-11-13

1994-02-15

Chun, Debra A.

Boots, shoes, and leggings

364DIG1, 364243, 36424341, 36424344, 36424345, 3642283, G06F 1208

Patent

active

052874842

ABSTRACT:
A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.

REFERENCES:
patent: 4464712 (1984-08-01), Fletcher
patent: 4939641 (1990-07-01), Schwartz
patent: 5056002 (1991-10-01), Watanabe
patent: 5058006 (1988-06-01), Durdan
Wescon Conference Record, "The NS32532-High Performance and Software Compatibility", V. 21, No. 3/4, Los Angeles, Calif., 1987, pp. 1-7.
IBM Technical Disclosure Bulletin, "Second Level Cache for NF Systems", IBM Corp., V. 27, No. 1A, Jun. 1884.
Alan J. Smith, "Cache Memories", ACM, Computing Surveys, vol. 14, No. 3, 1982, pp. 473-530 (provided in English).
Nikkei Electronics, Oct. 26, 1981, pp. 176-190 (English translation unavailable).
"Technical Research Report of the Institute of Electronics, Information and Communication Engineers of Japan", ICD 89-8-15, Apr. 21, 1989, pp. 29-36 (English translation unavailable).
James R. Goodman, "Using Cache Memory to Reduce Processor-Memory Traffic", 10th Annual International Symposium on Computer Architecture, 1983, pp. 124-131 (provided in English).

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