Method and device for correcting packet data error and packet re

Details Method and device for correcting packet data error and packet re Method and device for correcting packet data error and packet re

1996-12-10

1998-07-07

Baker, Stephen M.

Excavating

375365, H04L 708, H03M 1300

Patent

active

057780102

ABSTRACT:
A replacement control circuit 30, having a synchronization pattern monitoring circuit 31, an acquisition circuit 32, a tracking circuit 33, an RS flip-flop 34 and an AND gate 35, judges whether receive data D3 is in synchronization or not, counts a clock CLK corresponding to a byte of the receive data D3, and while the receive data D3 is judged to be in synchronization, generates a replacement control signal S5 that becomes active at a synchronization pattern location of each packet. When the replacement control signal S5 is active, a selection circuit 43 selects synchronization pattern P1 generated by a synchronization pattern generation circuit 42. When the replacement control signal S5 is inactive, the selection circuit 43 selects the receive data D3. The output of the selection circuit 43 is corrected by a byte error correction circuit in units of packets.

REFERENCES:
patent: 4649543 (1987-03-01), Levine
patent: 5610983 (1997-03-01), Stewart
"Code Theory", Hideki IMAI, Mar. 15, 1990.

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