Method and apparatus for parallel loads equalizing utilizing ins

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395800, 364DIG1, 3642624, 3642629, 3642287, G06F 1516

Patent

active

052874664

ABSTRACT:
A parallel processing system wherein the instruction field of each instruction is additionally provided with execution predict count information representative of the number of basic clocks required to execute the instruction, and sort circuits that rearrange a group of instructions on the basis of the execution predict count information are provided and wherein the group of instructions are divided into a plurality of blocks in units of columns, as a prefetching processing, and the blocks of instructions prefetched in units of columns are alternately subjected to sorting in descending order and sorting in ascending order by the sort circuits on the basis of the execution predict count information.

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