Method of making poly-sidewall contact transistors

Details Method of making poly-sidewall contact transistors Method of making poly-sidewall contact transistors

1988-05-09

1989-08-15

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 31, 437 89, 437 90, 437203, 437228, 437233, 156653, H01L 2136, H01L 2138

Patent

active

048574791

ABSTRACT:
Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lowest poly layer. The lateral epi-poly sidewall contacts are recessed under the intervening oxide layers to separate them from the active device regions in the center of the epi pillar.
The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. The exposed edges of the poly layers are oxidized. These edge oxide regions are removed in the holes where the device pillars are epitaxially grown. The remaining edge oxide regions isolate the buried conductor layers, contacts, and isolation walls. The polycrystalline pillar extending from the lowest poly layer to the device surface is formed at the same time as the epi-pillar. The structure is self-aligned and self-registering.

REFERENCES:
patent: 4157269 (1979-06-01), Ning et al.
patent: 4381953 (1983-05-01), Ho et al.
patent: 4396933 (1983-08-01), Magdo et al.
patent: 4462847 (1984-07-01), Thompson et al.
patent: 4578142 (1986-03-01), Corboy, Jr. et al.
patent: 4579621 (1986-04-01), Hine
patent: 4584025 (1986-04-01), Takaoka et al.
patent: 4592792 (1986-06-01), Corboy, Jr. et al.
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4696097 (1987-09-01), McLaughlin et al.
patent: 4710241 (1987-12-01), Komatsu
T. Nakamura et al, "Self-Aligned Transistor with Side-Wall Base Electrode", IEEE Solid-State Circuit Conference, 2-20-81, pp. 214-215.
T. Nakamura et al., "Self-Aligned Transistor with Side-Wall Base Electrode", IEEE Trans. on Electron Devices, vol. ED-29, No. 4, Apr. 82, pp. 596-600.
C. Cohen, "Upwardly Operating Bipolar Transistor Increase Efficiency", Electronics, Sep. 22, 82, pp. 85-86.

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