Method of manufacturing a semiconductor memory device

Details Method of manufacturing a semiconductor memory device Method of manufacturing a semiconductor memory device

1988-11-04

1989-08-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437 52, 437 67, 437 69, 437 72, 437228, 437 33, H01L 21265

Patent

active

048574783

ABSTRACT:
According to the present invention, a second conductivity type subcollector layer and a second conductivity type collector layer are sequentially formed on a first conductivity type semiconductor substrate and thereafter first and second insulation layers are simultaneously formed in a region corresponding to a memory element area and regions corresponding to prescribed regions of a peripheral circuit area within an upper layer part of the second conductivity type collector layer. Thus, the degree of integration is improved by simplification of manufacturing steps and reduction of the number of masking times.

REFERENCES:
patent: 4104086 (1978-08-01), Bomclur et al.
patent: 4238278 (1980-12-01), Amtipov
patent: 4434543 (1984-03-01), Schwabe et al.
patent: 4481704 (1984-11-01), Darley et al.
patent: 4509249 (1985-08-01), Goto et al.
patent: 4516316 (1985-05-01), Haskell
patent: 4536947 (1985-08-01), Bohn et al.
IEEE Cat. No. 85 CH 2125-3; 1985 Symposium on VLSI Technology (Digest of Technical Papers), May 14-16, 1985, Kobe, Japan.

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