Technique for reducing power consumption in digital filters

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G06F 1710

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active

057779147

ABSTRACT:
In a digital filter having tap coefficients, a gain element is employed to scale the filter output. The gain element is controlled by an error monitor element which runs an adaptive process in accordance with the invention. Such a process causes each tap coefficient value to be changed so as to reduce power consumption in the filter. On the other hand, the process ensures that the filter output maintains an acceptable signal to noise ratio (SNR), despite losing the bit precision of the filter as a result of the change of the coefficient values.

REFERENCES:
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patent: 5544201 (1996-08-01), Hoshino et al.
J. Ludwig et al., "Low-Power Digital Filtering Using Approximate Processing", IEEE Journal of Solid-State Circuits, vol. 31, No. 3, Mar. 1996, pp. 395-399.
M. Zheng et al., "Low Power and High Speed Multiplication Design through Mixed Number Representations", IEEE ICCD, 1995, pp. 566-570.
H. Choi et al., "Search-Based Wordlength Optimization for VLSI/DSP Synthesis", IEEE, 1994, pp. 198-207.

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