Patent
1983-06-16
1986-02-11
Clawson, Jr., Joseph E.
357 239, 357 2314, 357 54, 357 41, 357 42, H01L 2978
Patent
active
045701750
ABSTRACT:
At least one layer of insulator film and single-crystal film are alternately stacked and deposited on a surface of a semiconductor substrate, and an impurity-doped region formed in each semiconductor film is used as a gate, source or drain of a MOS transistor.
Thus, a three-dimensional semiconductor device is constructed in which MOS transistors are arranged, not only in the direction of the semiconductor substrate surface, but also in a direction perpendicular thereto.
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Garnache, R. R., "Complimentary FET Memory Cell", IBM Technical Disclosure Bulletin, vol. 18, No. 12, May 1976.
Colinge et al., "ST-CMOS: A Double-Poly-NMOS-Compatible CMOS Technology", Conference International Electron Device Meeting, Washington, DC (Dec. 1981).
Haruta Ryo
Kimura Shin'ichiro
Miyao Masanobu
Mukai Kiichiro
Nishioka Yasushiro
Clawson Jr. Joseph E.
Hitachi , Ltd.
Limanek Robert P.
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