Method for manufacturing field effect transistor

Details Method for manufacturing field effect transistor Method for manufacturing field effect transistor

1992-07-13

1994-02-15

Thomas, Tom

Fishing, trapping, and vermin destroying

437912, 437 22, 437 39, 437133, 148DIG82, H01L 21265

Patent

active

052866629

ABSTRACT:
A field effect transistor (FET) has a gate electrode, a source electrode and a drain electrode formed on a GaInAs/GaAs quantum well layer structure having an undoped GaAs layer, an impurity doped GaInAs layer, and an undoped GaAs cap layer. The FET further has low resistivity regions formed by ion-implantation in a source region and the drain region of the GaInAs/GaAs quantum well layer structure, and has the impurity doped GaInAs layer as a channel, and further has an undoped GaAs cap layer with a 30-50 nm thickness. An annealing temperature for activating the low resistivity region is not higher than a temperature at which the GaInAs/GaAs quantum well structure substantially breaks and not lower than a temperature at which the sheet resistivity of the low resistivity region sufficiently reduces. The FET thus manufactured has desired characteristics for the GaInAs/GaAs quantum well structure and the low resistivity region, and attains low noise and high speed operation.

REFERENCES:
patent: 5041393 (1991-08-01), Ahrens et al.

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