High speed to low speed data buffering means

Details High speed to low speed data buffering means High speed to low speed data buffering means

1980-10-24

1983-03-29

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1100

Patent

active

043785948

ABSTRACT:
A system is provided in which a memory is divided into two parts, so that a substantially continuous printing operation can be carried out by reading information to be printed from one part of the memory, with printing being interrupted for brief periods of time to permit writing of information in the other part of the memory. The writing into the memory is done on an alternate line basis, with the omitted lines being filled during a subsequent write operation so as to convert the interlace input to a standard format. At an appropriate time, the two parts of the memory are switched so that the read-out for the printing is carried out from the part into which information has just been written, and the writing takes place in the part of the memory which has been cleared during the preceding read operation.

REFERENCES:
patent: 3622701 (1971-11-01), Gardner
patent: 3739350 (1973-06-01), Moran
patent: 3869571 (1975-03-01), Delavie
patent: 4009332 (1977-02-01), Van Hook
patent: 4071910 (1978-01-01), Stockebrand et al.
patent: 4079458 (1978-03-01), Rider et al.
patent: 4125873 (1978-11-01), Chesarek

Affiliated with

Also associated with

Rating

High speed to low speed data buffering means does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed to low speed data buffering means, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed to low speed data buffering means will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1206046