Self aligned method to define features smaller than the resoluti

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

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216 41, 216 67, 438723, H01L 2100

Patent

active

057768366

ABSTRACT:
A first mask layer is deposited over a layer to be etched, which is itself situated on a semiconductor wafer. The first mask layer is then patterned by standard techniques using a given photolithography system, with a feature size at or near the resolution limit of the system employed, uncovering thereby a pattern on the layer to be etched. Next, a second mask layer is anisotropically deposited over the wafer surface, with the wafer surface tilted at a selected angle from the normal to the direction of the deposition. The angle is selected such that the first mask layer shields a portion of the pattern from the anisotropic stream of deposited material forming the second mask layer. The second mask layer thus deposits on only a portion of the previously uncovered pattern, leaving a remaining pattern having a feature size smaller than the resolution limit, or smaller than the smallest feature which can be printed, using the photolithography system employed. The layer to be etched is then etched with an etch process selective to the second mask layer. The first and second mask layers may then be removed, leaving the layer to be etched having a feature defined therein with a width smaller than the resolution limit of the photolithography system. The feature may be filled with a fill material, and the layer to be etched may then optionally be removed.

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patent: 5500080 (1996-03-01), Choi

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