Method of making a grooved gate structure of semiconductor devic

Details Method of making a grooved gate structure of semiconductor devic Method of making a grooved gate structure of semiconductor devic

1996-02-09

1998-07-07

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438723, H01L 2100

Patent

active

057768358

ABSTRACT:
A method is capable of providing a semiconductor device with a gate having thereon a thicker silicide or metal layer and further having a lower interconnect resistance. The method is further capable of providing the semiconductor device with a polysilicon gate having a recessed tungsten structure for prevention of short circuit between the gate and the drain or the source. For forming a grooved gate structure, a photo-resist is formed on the polysilicon gate before growing on the entire surface of the silicon substrate a silicon dioxide layer. The silicon dioxide layer and the thin gate oxidation layer on drain/source are etched vertically by a reactive ion etching until the photo-resist and the silicon surface of drain/source are exposed. A plurality of spacers are thus formed on the side walls of the photo-resist/polysilicon gate. Upon stripping the photo-resist, the grooved gate structure is formed on the semiconductor device.

REFERENCES:
Li-Rou Shiu, et al., "Novel Silicon Dielectric Selectively Deposited on Silicon Substrate," 1995 Annual Conference of the Chinese Society for Material Science, pp. 276-277, Apr. 21-22, 1995.
M. Sekine, et al., "Self-Aligned Tungsten Strapped Source/Drain and Gate Technology Realizing the Lowest Sheet Resistance for Sub-quarter Micron CMOS," 1994 IEEE IEDM digest abst. pp. 493-496.

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