Digital phase comparator with reset

Details Digital phase comparator with reset Digital phase comparator with reset

1977-01-14

1978-05-16

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307215, 307232, H03D 1300

Patent

active

040901432

ABSTRACT:
An all-channel PLL tuning system includes LOF counters, a comparator producing an equality pulse each time the LOF count matches a preselected channel number count and a digital phase-frequency comparator comparing the equality pulses with reference pulses. High speed tuning is accomplished with the phase-frequency comparator arranged to yield immediate correct directional information. A reset pulse is generated for every other equality pulse and forces the equality and reference pulses to have the same initial phase and the digital phase-frequency comparator into one of its stable states corresponding to the desired output condition. The output directional information from the phase comparator is stored and tuning proceeds at high speed until a change in directional information occurs, indicating that the correct tuning frequency has been passed. Normal PLL operation then ensues.

REFERENCES:
patent: 3501701 (1970-03-01), Reid
patent: 3610954 (1971-10-01), Treadway
patent: 3626307 (1971-12-01), Koyama
patent: 3755746 (1973-08-01), Hogue

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