Forced error generating circuit for a data processing unit

Details Forced error generating circuit for a data processing unit Forced error generating circuit for a data processing unit

1986-11-10

1988-10-18

Smith, Jerry

Excavating

G06F 1100

Patent

active

047792710

ABSTRACT:
A forced error generating circuit for a data processing unit comprises a forced error register for generating a designation signal to forcibly cause an error for a structural element in the data processing unit and a signal generating means which receives a signal for starting a period for causing the error by a forced error generating instruction and generates a forced error generating signal corresponding to said designation signal during said period.

REFERENCES:
patent: 3401379 (1968-09-01), Prell
patent: 4669081 (1987-05-01), Mathewes
D. G. East, "Error Injector for Testing a Data Processing Unit", IBM TDB, vol. 17, No. 6, Nov. 1974, pp. 1691-1692.
J. N. Gaulrapp, "Error Injector Tool", IBM TDB, vol. 20, No. 8, Jan. 1978, p. 3286.

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