1988-06-27
1989-04-25
Carroll, J.
357 41, 357 45, 357 51, 357 88, H01L 2978, H01L 2702, H01L 2710, H01L 2702
Patent
active
048252689
ABSTRACT:
A semiconductor memory device comprises a plurality of one-bit memory cells each having a MOS transistor and a MOS capacitor and arranged two-dimensionally. Of the memory cells along the column direction selected according to selection of a word line, adjacent cells are made different in the structure of cell capacitors. Such structural difference is realized by presence or absence of an impurity layer which has the same electrically-conductive type as a semiconductor substrate and higher in impurity concentration than the substrate between their storage nodes and the substrate, or by the difference in the surface area of the storage nodes when viewed from the substrate side, whereby when the semiconductor memory device is subjected to a single .alpha. ray at most one of the memory cells at least along the column direction causes a soft error.
REFERENCES:
patent: 4355374 (1982-10-01), Sakai et al.
Yamada et al., "A Submicron VLSI Memory with a 4b-at-a-Time Built-in ECC Circuit", ISSCC 84, Feb. 22, 1984, pp. 104-105.
Micron Technology, Inc., Technical Data Sheet on 256K DRAM.
Carroll J.
Kabushiki Kaisha Toshiba
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