Fast, efficient, small adder

Details Fast, efficient, small adder Fast, efficient, small adder

1981-10-27

1984-09-11

Shaw, Gareth D.

Boots, shoes, and leggings

364784, G06F 748, G06F 750

Patent

active

044714548

ABSTRACT:
A digital adder circuit is disclosed which employs non-DC current configurations to significantly reduce power, device count, and delay in performing binary addition. The circuit features a carry propagate transfer FET device whose gate is controlled by a carry propagate control circuit which selectively gates on the transfer FET device at a particular adder bit stage when the carry-in binary bit is to be transferred as the carry-out binary bit, which takes place when the augend input bit and addend input bit at that stage are not equal. The circuit additionally features a carry generate control circuit which is connected to the carry-out node of the FET transfer device, which selectively connects that node to either a drain potential when both inputs are unity or to ground potential when both inputs are zero, thereby efficiently generating the carry-out bit without regard for the state of the carry-in bit. When the input bits are not equal, the carry generate control circuit has a high impedance state so that it will not affect the propagation of the carry-in bit through the FET transfer device. The resultant adder circuit has a reduced power dissipation, a reduced signal delay, and a reduced device count when compared with prior art FET adder circuits.

REFERENCES:
patent: 3932734 (1976-01-01), Parjons
patent: 4010359 (1977-03-01), Weber et al.
patent: 4071905 (1978-01-01), Oguchi et al.
patent: 4110832 (1978-08-01), Leininger et al.
patent: 4272828 (1981-06-01), Negi et al.
patent: 4276608 (1981-06-01), Stakhov et al.
patent: 4422157 (1983-12-01), Uhlenhoff
patent: 4435782 (1984-03-01), Kaufman et al.

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