Vector processor with a synchronously controlled operand fetch c

Details Vector processor with a synchronously controlled operand fetch c Vector processor with a synchronously controlled operand fetch c

1984-12-21

1988-10-18

Shaw, Gareth D.

Boots, shoes, and leggings

364736, 364730, G06F 15347

Patent

active

047791926

ABSTRACT:
A vector processor for sequentially reading out elements of a plurality of vector operands and sequentially storing the results of operations to the vector operands, comprising: operand counters for indicating the element numbers for every operand; address registers for every operand; a first comparator for comparing each element of the vector; maximum number registers for storing the maximum numbers of elements of the respective operands; a second comparator for comparing the operand counter of each operand with the content of the maximum number registers of each operand with respect to each operand; and a control circuit for independently updating the operand counters and operand address registers of ech operand in response to all of or parts of the outputs of the first and second comparators.

REFERENCES:
patent: 3794984 (1974-02-01), Deerfield et al.
patent: 4172287 (1979-10-01), Kawabe et al.
patent: 4270181 (1981-05-01), Tanakura et al.
patent: 4293941 (1981-10-01), Muraoka et al.
patent: 4412285 (1983-10-01), Neches et al.
patent: 4525796 (1985-06-01), Omoda et al.
patent: 4641275 (1987-02-01), Hatakeyama et al.
patent: 4685076 (1987-08-01), Yoshida
P. M. Kogge, The Architecture of Pipelined Computers, 1981, chapter 5.2.8, pp. 204-207.

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