Test circuit of input architecture of erasable and programmable

Details Test circuit of input architecture of erasable and programmable Test circuit of input architecture of erasable and programmable

1991-09-25

1994-12-13

Beausoliel, Jr., Robert W.

Excavating

371 221, 36496576, H04B 1700, G06F 900

Patent

active

053735102

ABSTRACT:
In accordance of the invention, the Erasable and Programmable Logic Device comprising a test circuit of the input architectures is provided.
The test circuit comprises an extra test line 39, a plurality of EPROM transistors 34 having respectively the drain thereof connected to the extra test line and the gate thereof connected to a true input line provided from said one input architecture, sensing means 36 connected to the extra test line for sensing the state of the extra test line, and a buffer circuit 37 connected to the sensing means.

REFERENCES:
patent: 4393474 (1983-06-01), McElroy
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartman et al.
patent: 4713792 (1987-12-01), Hartman et al.
patent: 4749947 (1988-06-01), Gheewala
patent: 4972144 (1990-11-01), Lyon et al.

Affiliated with

Also associated with

Rating

Test circuit of input architecture of erasable and programmable does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test circuit of input architecture of erasable and programmable , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test circuit of input architecture of erasable and programmable will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1198092