Low-power consumption simple row addressing system incorporated

Details Low-power consumption simple row addressing system incorporated Low-power consumption simple row addressing system incorporated

1993-05-26

1994-12-13

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523001, 365203, 36518911, 365205, G11C 700

Patent

active

053734793

ABSTRACT:
A row addressing system is responsive to row address bits for selecting one of row addresses respectively assigned to word lines, and comprises a row address buffer unit for producing row address predecoded signals from said row address bits, a word line driving unit responsive to a row address decoded signal for selectively driving the word lines and a row address decoder unit including a plurality of row address decoder circuits coupled between the row address buffer unit and the word line driving unit, wherein each row address decoder circuit has a flip flop circuit coupled between a boosted voltage line and a pair of output nodes for maintaining voltage levels at the pair of output nodes, a reset circuit coupled between one of the output nodes and a ground voltage line and responsive to a precharging signal of a power voltage level for charging the other output node to the boosted voltage level, and a decoder coupled between the other output node and the ground voltage line and responsive to the row address predecoded signals for producing the row address decoded signal so that the precharging signal of the power voltage level decreases current consumption without sacrifice of simple circuit arrangement.

REFERENCES:
patent: 4503522 (1985-03-01), Etoh et al.
patent: 4704706 (1987-11-01), Nakano et al.
IBM TDB, "High performance complementary decoder/driver circuit", vol. 29, No. 6, Nov./1986, pp. 2390-2394.
K. Komatsuzaki et al., "Circuit Techniques For a Wide Word I/O Path 64 Meg DRAM", pp. 133-134.

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