DRAM controller

Details DRAM controller DRAM controller

1991-02-21

1992-10-06

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365222, 36518904, G11C 1300

Patent

active

051538563

ABSTRACT:
A DRAM controller comprises an address output controller for transferring an address-designating signal to a dynamic RAM, a data output controller for transferring data to be written into and read-out from a memory region of the dynamic RAM which is designated by the address-designating signal, and a control circuit responsive to a mode-designating signal for generating various control signals corresponding to an access mode of the dynamic RAM designated by the mode-designating signal and for supplying control signals to the dynamic RAM, address output controller, and data output controller in a predetermined sequence. In the DRAM controller, the control circuit includes a signal-generating unit for generating control signals in a specific access mode which requires an access time longer than a machine cycle of a processor for generating the address-designating signal, the data to be written, and the mode-designating signal, the signal-generating means delaying generation control signals every time designation of the specific access mode by the mode-designating signal is repeated.

REFERENCES:
patent: 4660180 (1987-04-01), Tanimura et al.
IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989, pp. 310-312, Programmable Pulse Sequence Control of Dynamic RAMS.
Hitachi Review, vol. 35, No. 5, Oct. 1986, pp. 255-258, 1 Mbit Dynamic RAM "HM511000 Series".
Patent Abstracts of Japan, vol. 012, No. 408, Oct. 1988, Control System for Dynamic RAM.

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