Fishing – trapping – and vermin destroying
Patent
1987-10-02
1989-04-25
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437201, 437187, 437245, 437228, H01L 21283, H01L 21312
Patent
active
048248029
ABSTRACT:
A method compatible with very large scale integrated circuit fabrication processes is employed to provide an electrical connection between conductive layers separated by an insulative layer in integrated circuit devices. An intermediary metal such as molybdenum or tungsten is deposited by one or more methods so as to fill an opening in the insulative layer. A planarization resist may be applied on the substrate and the resulting configuration is planarizingly etched down to the insulative layer so as to provide a metal plug conductive layers. Deposition is by sputtering, evaporation, or by either selective or non-selective chemical vapor deposition. The process and structure provided herein significantly alleviates step coverage problems associated with aluminum and like materials which do not readily penetrate small VLSI circuit openings.
REFERENCES:
patent: 4520041 (1985-05-01), Aoyama et al.
Parry et al, "Anisotropic Plasma et Cling . . . ", Solid State Technology, Apr. 1979, pp. 125-132.
Moziya et al, "A Planar Metallization Process", IEDM Technical Digest, 1983, pp. 550-553.
Ghandhi, YLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 498-517.
Brown Dale M.
Gorowitz Bernard
Saia Richard J.
Davis Jr. James C.
General Electric Company
Hearn Brian E.
Ochis Robert
Quach T. N.
LandOfFree
Method of filling interlevel dielectric via or contact holes in does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of filling interlevel dielectric via or contact holes in , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of filling interlevel dielectric via or contact holes in will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1195712