Layout of large multistage interconnection networks technical fi

Details Layout of large multistage interconnection networks technical fi Layout of large multistage interconnection networks technical fi

1988-04-01

1992-10-06

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

051538431

ABSTRACT:
A technique for laying out large multistage interconnection networks. The invention provides for the division of a network into sub-networks which may be maintained on printed circuit boards and then provides for the addition of switching circuitry at the inputs or outputs of such boards such that pin locations on the boards may be swapped with each other to allow for a parallel interconnection of corresponding pins between the boards. Such parallel interconnection eliminates the existence of rat's nests in the wiring harness.

REFERENCES:
patent: 3681782 (1972-08-01), Scanlon
patent: 3705409 (1972-12-01), Brayton et al.
patent: 3800289 (1974-03-01), Batcher
patent: 4495559 (1985-01-01), Gelatt, Jr. et al.
patent: 4593363 (1986-06-01), Burstein et al.
"Outline of Interactive Printed Substrate Design System and Automatic Layout Procedure" by K. Daishidow et al., 30th National Conference of the Information Processing Society of Japan, pp. 1901-1903, 1985.
"Binary Decision Diagrams" by S. B. Akers, IEEE Transaction on Computers, vol. c-27, No. 6, Jun. 1978, pp. 509-517.

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