Protective circuit on insulating substrate for protecting MOS in

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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361 91, 357 50, 357 47, H02H 320

Patent

active

042888298

ABSTRACT:
A MOS integrated circuit comprises a MOS IC body including at least one MOS transistor made of an island-like semiconductor layer formed on an insulating substrate, and a protective circuit connected between a signal input terminal and the gate electrode of a MOS transistor at least at an input stage of the MOS IC body and adapted to protect the MOS integrated circuit against an irregular input signal. The protective circuit is also connected between ground and the gate electrode of the MOS transistor at the input stage of the MOS IC body and comprises a protective MOS transistor made of an island-like semiconductor layer formed on the insulating substrate in a manner to be arranged in juxtaposition with the MOS transistor at the input stage of the MOS IC body, a resistor connected between the signal input terminal and the gate circuit of the MOS transistor as the input stage of the MOS IC body the resistor being formed on a grounded insulating layer on the semiconductor layer overlying the insulating substrate to provide a stray capacitance therebetween, the resistor being formed in juxtapositon with the protective MOS transistor.

REFERENCES:
patent: 3403270 (1968-09-01), Pace et al.
patent: 3636418 (1972-01-01), Burns
patent: 3712995 (1973-01-01), Steudel
patent: 3728591 (1973-04-01), Sunshine
patent: 3967295 (1976-06-01), Stewart
patent: 4042948 (1977-08-01), Kilby
patent: 4092735 (1978-05-01), McElroy

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