Fishing – trapping – and vermin destroying
Patent
1987-06-10
1988-10-18
Hearn, Brian E.
Fishing, trapping, and vermin destroying
357 237, 437187, 437 43, H01L 21265, H01L 2144
Patent
active
047787732
ABSTRACT:
A method of manufacturing a thin film transistor comprises the steps of forming a gate electrode on one surface of a transparent substrate, forming on the substrate an insulating layer and a semiconductor layer in the named order to cover the gate electrode, and depositing a positive photoresist layer on the semiconductor layer. Thereafter, the photoresist layer is exposed by irradiating from the other surface of the substrate so as to use the gate electrode as a mask. Therefore, if the positive photoresist layer is developed, the unexposed portion remains on the semiconductor layer to correspond to the gate electrode. Then, the semiconductor layer is etched using the remaining photoresist as a mask so as to form a semiconductor island on the insulating layer, and source and drain electrodes are formed on the semiconductor island.
REFERENCES:
patent: 4700458 (1987-10-01), Suzuki
Ghandhi, VLS1 Fabrication Principles, John Wiley and Sons, Inc., 1983, pp. 542-550 and 582-585.
Kodama et al., "A self-Alignment Process for Amorphous Silicon Thin Film Transistors", IEEE Electron Device Letters, vol. EDL-3, No. 7, Jul. 1982, pp. 187-189.
Kawai et al., "A Self-Alignment Processed a-Si:H TFT Matrix Circuit for LCD Panels", Proceedings of the SID, vol. 25/1, 1984, pp. 21-24.
Hearn Brian E.
NEC Corporation
Wilczewski M.
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