Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Patent
1989-08-18
1992-10-06
Groody, James J.
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
H04N 514
Patent
active
051537265
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
This invention concerns the storage and editing of moving television pictures, and more especially to the storage of television pictures in digital form in solid state random access memory chips, to enable digital television pictures to be retrieved from the store for editing.
Although systems exist that enable the storage of individual television frames in memory stores to enable the modification of the television images for the production of so-called digital video effects, the capacity of available stores is such that only a very limited number of individual image frames can be stored at a given time.
Therefore, where it is desired to record and edit moving television pictures, the current state of the art requires that such moving pictures be recorded on magnetic or optical tapes or discs and subsequently replayed to enable editing to be carried out. Such systems, however, all suffer from the drawback that mechanical movement of the recording medium is required, that a significant amount of time is taken in moving the medium or access mechanism when it is desired to replay a different portion of the recording and that only one point on the recording can be replayed at any one time.
SUMMARY OF THE INVENTION
In accordance with the present invention it is proposed to utilise the ever larger random access memory devices that are now becoming available to store significantly larger numbers of frames of picture image information, with the object of providing an all-electronic moving picture recorder which is capable of recording, replaying and editing several minutes of moving television pictures without the use of mechanical moving parts. Such a system may store the picture information entirely in random access memory chips and be capable of reading and writing in several places at once in the store so that it can be used as a replacement for several video tape or disc recorders at once.
The system to be described below uses devices organised as 1 Megabit.times.1 dynamic, however, it is possible to use other devices such as static or semi-static devices and other device sizes.
Before it is stored the picture information must first be sampled or broken up into discrete elements known as pixels. In the system to be described this is done according to the standard known as the 4:2:2 standard or the CCIR 601 standard, however this is not necessary and the invention could be realised by means of a variety of different sampling systems.
In accordance with one aspect of the invention a memory store for receiving digital television picture signals to be transmitted thereto in serial form comprises a plurality of memory storage sub-systems each incorporating a corresponding input/output buffer, the said sub-systems being connected in parallel to data and control signal buses and control means being provided for presenting to said control buses addressing and read and/or write signals for the storage and/retrieval of said serial picture signal, the arrangement being such that adjacent groups of data bits of said serial signal are distributed between the respective sub-systems whereby each bit of each group is assigned to a corresponding memory address in a respective one of said sub-systems.
Thus, by applying to all of said sub-systems common addressing signals identifying the respective groups of data bits, together with read or write signals that cause the buffers of the respective sub-systems to respond in sequence at the repetition rate of the data-bits, a serial data signal can be stored in the sub-systems in real time, whilst the time required for storage of each data bit in a corresponding memory sub-system is increased in relation to the repetition rate of the data bits by a factor corresponding to the number of sub-systems.
BRIEF DESCRIPTION OF THE DRAWINGS
A system in accordance with the invention is illustrated by way of example in the accompanying drawing, the single figure of which is a block diagram showing the organisation of a solid state memory enabling the reading
REFERENCES:
patent: 4437121 (1984-03-01), Taylor et al.
patent: 4450538 (1984-05-01), Shirasaka
patent: 4485402 (1984-11-01), Searby
patent: 5023718 (1991-06-01), Soloff
1986 IEEE International Solid-State Circuits Conference, Digest of Technical Data Papers, Feb. 21, 1986.
IEEE, Ohta et al.: "A 1 Mb DRAM with 33 MHz Serial I/O Ports", pp. 274-275.
Groody James J.
Harvey David E.
Questech Limited
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