1991-03-28
1992-10-06
Lee, John D.
H01L 2972
Patent
active
051536927
ABSTRACT:
In a semiconductor device, a depletion region is provided in a part of an emitter region by pinning Fermi level at Schottky junction or an interface with a high-resistivity semiconductor layer or surface thereof. The depletion region is extended throughout a full thickness of the emitter layer, thereby to prevent electrons from being diffused in the direction of the interface with the high-resistivity semiconductor layer so as to recombine through crystalline defects. Thus, the current gain of the device is greatly increased.
REFERENCES:
Lin et al.; "Super-Gain AlGaAs/GaAs Heterojunction Bipolar Transistors Using an Emitter Edge-Thinning Design"; Appl. Phys. Letters; vol. 47, No. 8, Oct. 1985; pp. 839-841.
W.-S. Lee et al., "Effect of Emitter-Base Spacing on the Current Gain of AlGaAs/GaAs Heterojunction Bipolar Transistors", IEEE Electron Device Letters, vol. 10, No. 5, May 1989, pp. 200-202.
O. Nakajima et al., "High-Performance AlGaAs/GaAs HBT's Utilizing Proton-Implanted Buried Layers and Highly Doped Base Layers", IEEE Transactions on Electron Devices, vol. ED-34, No. 12, Dec. 1987, pp. 2393-2398.
Kabushiki Kaisha Toshiba
Lee John D.
Wise Robert E.
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