Semiconductor memory device having bit lines formed of an interc

Details Semiconductor memory device having bit lines formed of an interc Semiconductor memory device having bit lines formed of an interc

1989-09-08

1992-10-06

James, Andrew J.

357 234, H01L 2978

Patent

active

051536897

ABSTRACT:
A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

REFERENCES:
patent: 4754313 (1988-06-01), Takemae et al.
patent: 4810619 (1989-03-01), Pampalone et al.
Sze, Semiconductor Devices, 1985, pp. 376-377.
M. Koyanagi et al., "Novel High Density, Stacked Capacitor MOS RAM" IEDM 1978, pp. 348-351.
IEEE Journal of Solid-State Circuits, vol. SL-15, No. 4, Aug. 1980, by Koyamagi et al., pp. 661-666, "A 5-V Only 16-kbit Stacked-Capacitor MOS RAM".
IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, by Saito et al., pp. 903-908, "A I-Mbit CMOS DRAM with Fast Page Mode and Static Column Mode".
Electronics, Aug. 25, 1982, by W. C. Benzing, pp. 116-119 "Shrinking VLSI dimensions demand new interconnection materials".
IBM Technical Disclosure Bulletin, vol. 22, No. 12, No. 12, May 1980, pp. 5466-5467 "Improved Conductivity Polysilicon Lines for MOSFET and Bipolar Technology" by B. L. Crowder and S. Zirinsky.

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