System for defeating erroneous correction in a digital signal re

Details System for defeating erroneous correction in a digital signal re System for defeating erroneous correction in a digital signal re

1981-03-10

1984-04-24

Malzahn, David H.

Excavating

G06F 1110

Patent

active

044452160

ABSTRACT:
A system for defeating erroneous correction in a digital signal reproducing apparatus. The system includes a reproducing circuit for reproducing a signal sequence in which information words and error correcting words are interleaved. A memory stores the reproduced digital signal sequence and produces a digital signal sequence made up of the information words and error correcting words, which are then de-interleaved and arranged in an original sequence. A correcting circuit corrects adjacent errors with respect to the digital signal sequence produced from the memory. A digital-to-analog converter converts a digital information signal obtained from the correcting circuit into an original analog information signal. The correcting circuit calculates partial syndromes according to predetermined equations and detects the number of erroneous words in one block which is made up of interleaved words. The error correcting operation is stopped when there are certain set of conditions which are related to the values of the partial syndromes and when the number of erroneous words are satisfied. The system continues to stop the correcting operation until other sets of conditions are satisfied, in order to correct errors of up to two words in each of the blocks made up of the de-interleaved words.

REFERENCES:
patent: 4151510 (1979-04-01), Howell et al.
patent: 4281355 (1981-07-01), Wada et al.
patent: 4306305 (1981-12-01), Doi et al.
patent: 4330860 (1982-05-01), Wada et al.
IBM J. Res. Develop., vol. 24, No. 1, pp. 32-42.

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