Information handling system for modifying coherency response set

Details Information handling system for modifying coherency response set Information handling system for modifying coherency response set

1995-09-29

1998-08-04

Lee, Thomas C.

395468, 395825, 395849, 395860, G06F 1300

Patent

active

057908923

ABSTRACT:
An information handling system includes a number of processors, each connected to a processor bus, a memory controller connected to the processor bus which controls access to a system memory, a system controller, and one or more I/O controllers connected to the system bus where the system controller controls access to the system bus by all of the elements connected to the system bus, and the memory controller provides an efficient mechanism for handling data access to memory on read commands if a coherency response is modified. Combiner-prioritization logic in the memory controller includes logic in response to two additional inputs not shown in the prior art. The first logic responds to a read command and signals when a response window currently being combined is from a read command, and the second logic signals that the memory has an intervention buffer available to allow intervention.

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