System with reservation instruction execution to store branch ta

Details System with reservation instruction execution to store branch ta System with reservation instruction execution to store branch ta

1996-02-21

1998-08-04

Kim, Kenneth S.

395706, 395708, 395383, 395584, G06F 938

Patent

active

057908451

ABSTRACT:
To improve the efficiency of instruction branch operations, particularly in a pipeline processor, a branch reservation instruction is generated during program compile. The system includes a processor having a branch address stack 10 for storing pairs of branch point addresses and branch target addresses, a program counter (PC) 12 which holds a current instruction fetch address, a comparator 11 which compares the branch point address of the most recently entered pair stored in the stack 10 and the value of the PC 12, and a selector 14 which, when the result of comparison shows the coincidence, switches the instruction fetch address from the value of the PC 12 to the branch target address of the most recently entered pair stored in the stack 10. The branch operation is performed by reserving a pair of a branch target address and a branch point address in the stack 10 by a branch reservation instruction in advance of the branch point in the instruction sequence, and switching the next instruction fetch address to the branch target address promptly when the instruction fetch reaches the branch point.

REFERENCES:
patent: 5142634 (1992-08-01), Fite et al.
patent: 5237666 (1993-08-01), Suzuki et al.
patent: 5530825 (1996-06-01), Black et al.
patent: 5592634 (1997-01-01), Circello et al.
patent: 5606676 (1997-02-01), Grochowski et al.
patent: 5615386 (1997-03-01), Amerson et al.
Computer Architecture: A Quantitative Approach, 1990, J.L. Hennessy et al Morgan Kaufmann Publishers, chapter 6.

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