Patent
1996-08-20
1998-08-04
Butler, Dennis M.
395556, 395559, G06F 104
Patent
active
057908389
ABSTRACT:
According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended for use with Level 2 and Level 3 cache SRAM memory devices. In the present invention, the oscillator that generates the clock signal for the CPU is also used to generate the clock signals for all of the other components that interface with the SRAM. Each of the generated clock signals are dependant on the same clock event, allowing the clock speed to be decreased for testing or debugging while maintaining higher speed clock edge relationships. The various clock signals that are generated from the oscillator are used to cycle-steal time from multiple cycles. This technique allows sub-5 nanosecond (nS) access to Level 2 and Level 3 cache memory devices that have access times greater than 5 nS.
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Irish John David
Johnson Charles Luther
Krolak David John
Levenstein Sheldon Bernard
Butler Dennis M.
International Business Machines - Corporation
Martin Derek P.
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