Patent
1996-09-30
1998-08-04
Chan, Eddie P.
395440, 395441, 395464, 395412, G06F 1202, G06F 1210, G06F 1316
Patent
active
057908281
ABSTRACT:
A data processing system which includes a processor having a processor memory and a mechanism for specifying an address that corresponds to a processor-requested data block located within another memory to be accessed by the processor. A hierarchical memory system is provided, which includes a cache and a long-term storage. An address of a requested data block is translated to a second addressing scheme, and is meshed, so that proximate data blocks are placed on different physical target disks within the long-term storage. A user-configuration mechanism is provided, which allows the user to define one or more user-configurable parameters which will control the access to the cache, and the transfer of data between the processor and the cache and between the cache and the long-term storage.
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Bragdon Reginald G.
Chan Eddie P.
Southwestern Bell Technology Resources, Inc.
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