Boots – shoes – and leggings
Patent
1982-09-30
1985-06-11
Thomas, James D.
Boots, shoes, and leggings
G06F 946, G06F 932, G06F 942
Patent
active
045232776
ABSTRACT:
A high speed priority interrupt system which permits a microcomputer to service a plurality of peripheral units on a priority basis is provided. Interrupt address jump vectors corresponding to the routines for servicing the peripheral devices are stored in a read only memory and are selectively transferred to a program counter in accordance with a predetermined priority basis to allow the microcomputer to interrupt its program and service one or more peripheral devices requesting access to the microcomputer. The interrupt system minimizes the time required by the microcomputer for interruption of the current program, servicing of the peripheral units, and resumption of the interrupted program.
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Martha E. Sloan, Computer Hardware and Organization: An Introduction, (Science Research Associated, Inc., 1976), pp. 378-386.
Intel 8080 Microcomputer Systems User's Manual, (Intel Corp., Sep. 1975), pp. 1-4, 2-11, 5-173, 5-174, 5-153 to 5-162.
Cavender J. T.
Lee Thomas
NCR Corporation
Salys Casimer K.
Thomas James D.
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