Method and apparatus for finite field multiplication

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

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G06F 700

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060498153

ABSTRACT:
A method of computing the product D of two finite field elements B and C modulo an irreducible polynomial f.sub.1 (x), wherein the finite field elements B and C are represented in terms of an optimal normal basis (ONB) of Type 1 over a field F.sub.2.spsb.n and the irreducible polynomial f.sub.1 (x) being of degree n, which comprises the steps of representing the element B as a vector of binary digits b.sub.i, where b.sub.i is a co-efficient of an i.sup.th basis element of the ONB representation of element B, in polynomial order, representing the element C as a vector of binary digits c.sub.i, where c.sub.i is a co-efficient of an i.sup.th basis element of the ONB representation of element C, arranged in polynomial order, initializing a register A, selecting a digit c.sub.i of the vector C, computing a partial product vector A of the i.sup.th digit c.sub.i of the element C and the vector B, adding the partial product to the register A, shifting the register A, reducing the partial product A by a multiple f.sub.2 (x) of the irreducible polynomial f.sub.1 (x) if bits in a position above n are set, storing the reduced partial product in the register A, repeating for each successive bit of the vector C and upon completion the register A containing a final product vector; and reducing the final product vector A by the irreducible polynomial f.sub.1 (x) if an n.sup.th bit of the register is set. The reduction step by the multiple of the irreducible polynomial simply involves a shift operation performed on the partial products.

REFERENCES:
patent: 4162480 (1979-07-01), Berlekamp
patent: 4165444 (1979-08-01), Gordon
patent: 4797921 (1989-01-01), Shiraishi
patent: 5313530 (1994-05-01), Iwamura
patent: 5642367 (1997-06-01), Kao

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