Method for generating test patterns for use with a scan circuit

Details Method for generating test patterns for use with a scan circuit Method for generating test patterns for use with a scan circuit

1992-10-26

1996-12-24

Voeltz, Emanuel T.

Excavating

371 223, 371 226, 371 24, H04B 152

Patent

active

055880088

ABSTRACT:
A method for generating a test pattern for use with a scan circuit utilized in detecting a degenerative failure in a synchronous sequential circuit including a memory element unit, having a scan register, and a combination circuit unit for receiving an external input and inputting a value from the memory element unit, and for supplying an external output and outputting a value to the memory element unit. The method includes generating, for an undetected failure, a test pattern for use in a combinational circuit. The method also includes generating a test pattern series for detecting a different failure by observing its external output value and by changing the external input value with the value set in a scan register of the memory element unit.

REFERENCES:
patent: 4687988 (1987-08-01), Eichelberger et al.
patent: 4716564 (1987-12-01), Hung et al.
patent: 4728883 (1988-03-01), Green
patent: 4744047 (1988-05-01), Okamoto et al.
patent: 4745355 (1988-05-01), Eichelberger et al.
patent: 4754215 (1988-06-01), Kawai
patent: 4775977 (1988-10-01), Dehara
patent: 4779273 (1988-10-01), Beucler et al.
patent: 4801870 (1989-01-01), Eichelberger et al.
patent: 4862460 (1989-08-01), Yamaguchi
patent: 4931723 (1990-06-01), Jeffrey et al.
patent: 5010552 (1991-04-01), Dias et al.
patent: 5127010 (1992-06-01), Satoh
patent: 5130647 (1992-07-01), Sakashita et al.
patent: 5132974 (1992-07-01), Rosales
patent: 5155432 (1992-10-01), Mahoney
patent: 5159600 (1992-10-01), Chintapalli et al.
patent: 5175494 (1992-12-01), Yoshimori
patent: 5239262 (1993-08-01), Grutzner et al.
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 5291495 (1994-03-01), Udell, Jr.
patent: 5297151 (1994-03-01), Grutzner et al.
patent: 5430736 (1995-07-01), Takeoka et al.

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