Nonvolatile memory device having program and/or erase voltage cl

Details Nonvolatile memory device having program and/or erase voltage cl Nonvolatile memory device having program and/or erase voltage cl

1999-08-03

2000-04-11

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 36518523, 36518529, G11C 1614

Patent

active

060494832

ABSTRACT:
Circuits for applying a programming voltage and erase voltage to memory cells in a nonvolatile memory device are disclosed. The reverse breakdown of p-n junctions within the memory cells is prevented by providing a clamping p-n junction in the path used to apply the program or erase voltage to the memory cells. The clamping p-n junction will breakdown before the p-n junctions within the memory cells, protecting the memory cells from the adverse effects of a reverse breakdown condition.

REFERENCES:
patent: 4718041 (1988-01-01), Baglee et al.
patent: 4763305 (1988-08-01), Kuo
patent: 4805151 (1989-02-01), Terada et al.

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