Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-11-12
1999-10-05
Nguyen, Viet Q.
Static information storage and retrieval
Floating gate
Particular biasing
36518533, 36518509, 365218, 36523003, 365236, 365200, 3651853, G11C 700
Patent
active
059634804
ABSTRACT:
Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
REFERENCES:
patent: 4051354 (1977-09-01), Choate
patent: 4087795 (1978-05-01), Rossler
patent: 4093985 (1978-06-01), Das
patent: 4181980 (1980-01-01), McCoy
patent: 4279024 (1981-07-01), Schrenk
patent: 4287570 (1981-09-01), Stark
patent: 4357685 (1982-11-01), Daniele et al.
patent: 4422161 (1983-12-01), Kressel et al.
patent: 4430727 (1984-02-01), Moore et al.
patent: 4448400 (1984-05-01), Harari
patent: 4460982 (1984-07-01), Gee et al.
patent: 4493075 (1985-01-01), Anderson et al.
patent: 4525839 (1985-07-01), Nozawa et al.
patent: 4527251 (1985-07-01), Nibby, Jr. et al.
patent: 4528683 (1985-07-01), Henry
patent: 4562532 (1985-12-01), Nishizawa et al.
patent: 4608671 (1986-08-01), Shimizu et al.
patent: 4612640 (1986-09-01), Mehrotra et al.
patent: 4616311 (1986-10-01), Sato
patent: 4617651 (1986-10-01), Ip et al.
patent: 4638457 (1987-01-01), Schrenk
patent: 4652897 (1987-03-01), Okuyama et al.
patent: 4663770 (1987-05-01), Murray et al.
patent: 4667217 (1987-05-01), Janning
patent: 4682287 (1987-07-01), Mizuno et al.
patent: 4718041 (1988-01-01), Baglee et al.
patent: 4733394 (1988-03-01), Giebel
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4763305 (1988-08-01), Kuo
patent: 4774700 (1988-09-01), Satoh et al.
patent: 4800520 (1989-01-01), Iijima
patent: 4803707 (1989-02-01), Cordan
patent: 4860228 (1989-08-01), Carroll
patent: 4887234 (1989-12-01), Iijima
patent: 4888686 (1989-12-01), Sinz et al.
patent: 4896262 (1990-01-01), Wayama et al.
patent: 4942556 (1990-07-01), Sasaki et al.
patent: 4949240 (1990-08-01), Iijima
patent: 5016215 (1991-05-01), Tigelaar
patent: 5043940 (1991-08-01), Harari
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5222109 (1993-06-01), Pricer
patent: 5268870 (1993-12-01), Harari
patent: 5270979 (1993-12-01), Harari et al.
patent: 5293560 (1994-03-01), Harari
patent: 5369615 (1994-11-01), Harari et al.
patent: 5396468 (1995-03-01), Harari et al.
patent: 5414664 (1995-05-01), Lin et al.
patent: 5535328 (1996-07-01), Harari et al.
patent: 5544118 (1996-08-01), Harari
patent: 5554553 (1996-09-01), Harari
patent: 5568439 (1996-10-01), Harari
patent: 5642312 (1997-06-01), Harari
patent: 5712819 (1998-01-01), Harari
patent: 5835415 (1998-11-01), Harari
patent: 5862081 (1999-01-01), Harari
M. Stark, "Two Bits Per Cell ROM", Digest of Papers VLSI, 1981, pp. 209-212.
Torelli et al., "An Improved Method for Programming a Word-Erasable EEPROM," Alta Frequenza, vol. 52, No. 5, Nov. 1983, pp. 487-494.
Harold, "Production of E.P.R.O.M. Loading," New Electronics, vol. 15, No. 3, Feb. 1982, pp. 47-50.
Torelli, "An LSI Technology Fully Compatible EAROM Cell," Alta Frequenza, No. 6, vol. LI, pp. 345-351 (1982).
Lucerno et al., "A 16kbit Smart 5 V-Only EEPROM with Redundancy", IEEE Journal of Solid State Circuits, vol. SC-18, No. 5, pp. 539544 Oct. 1983.
Berenga et al., "E2-PROM TV Synthesizer," 1978 IEEE ISSCC Digest of Technical Papers, Sec 039463, pp. 196-197, Feb. 1978.
"Japanese Develop Nondestructive Analog Semiconductor Memory," Electronics Review, Jul. 11, 1974, p. 29.
Alberts et al., Multi-Bit Storage FET EAROM Cell, IBM Technical Disclosure Buletin, vol. 24, No. 7A, Dec. 1981, p. 3311.
Horiguchi et al., An Experimental Large-Capacity Semiconductor File Memory Using 16-Levels/Cell Storage', IEEE Journal of Solid-State Circuits, Feb. 1988, p. 27-33.
Bleiker et al., "A Four-State EEPROM Using Floating-Gate Memory Cells," IEEE Journal of Solid-State Circuits, Jul. 1987, p. 460-463.
Furuyama et al., "An Experimental 2 Bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Applications," IEEE Custom Integrated Circuits Conference, May 1988, p. 4.4.1.
LandOfFree
Highly compact EPROM and flash EEPROM devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Highly compact EPROM and flash EEPROM devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Highly compact EPROM and flash EEPROM devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1179406