Flash EPROM erase algorithm with wordline level retry

Details Flash EPROM erase algorithm with wordline level retry Flash EPROM erase algorithm with wordline level retry

1997-12-09

1999-10-05

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518511, 36518523, 36518529, 365201, 365218, 36523003, 36523006, G11C 700, G11C 1600

Patent

active

059634774

ABSTRACT:
Methods and systems for floating gate memory cell array erasure with wordline level retry are disclosed. A data storage device includes a memory array organized into a plurality of blocks of memory cells, each of the blocks including a plurality of wordlines of memory cells. An energizing circuit applies energizing voltages to the memory cells to read and program addressed cells, and to erase selected blocks of memory cells, or the whole memory array. An erase verify circuit separately verifies erasure of the individual wordlines that compose each block that is erased. The control logic can include a plurality of shared wordline erase flags which correspond to respective wordlines in each particular block as they are verified. If the wordline passes erase verify, then the wordline erase flag is reset. Only those wordlines having a set wordline erase flag after the erase verify operation are re-erased. To support this operation, the circuit includes the capability of erasing only a single wordline of the memory array at a time. The invention provides the advantages of higher speed of erasure and enhanced protection against over erasure.

REFERENCES:
patent: 4875188 (1989-10-01), Jungroth
patent: 5414664 (1995-05-01), Lin et al.

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