Programmable controller in which fetching of operand data and fe

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364DIG1, 364187, 364132, 364133, 364136, 364243, 3642433, 395425, G06F 1300

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051650266

ABSTRACT:
A program memory and a data memory are independently arranged, and a holding register is arranged between the program memory and the data memory. The program memory and the holding register, the holding register and the data memory, and the data memory, a bit computation unit, and a numerical computation unit are respectively connected to each other through independent buses. After an operand address output from the program memory is latched by the holding register, the content of an instruction pointer for the program memory is updated. As a result, since an operand of the next instruction is set in a register file upon completion of execution of the first instruction, a processing speed can be increased.

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patent: 4663730 (1987-05-01), Ikeda
patent: 4700292 (1987-10-01), Campanini
patent: 4882702 (1989-11-01), Struger et al.

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