Programmable delay circuit having calibratable delays

Details Programmable delay circuit having calibratable delays Programmable delay circuit having calibratable delays

1997-06-18

1999-10-05

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327284, 327277, H03K 513

Patent

active

059630744

ABSTRACT:
A programmable delay circuit produces an OUTPUT signal following an INPUT signal with a delay selected by input delay selection data. The delay circuit includes a tapped delay line, a multiplexer, a delay adjustment stage and a programmable encoder. The delay line includes a set of N delay elements connected in series for successively delaying the INPUT signal to produce a set of N output TAP signals. The multiplexer passes a selected TAP signal to the delay adjustment stage. The delay adjustment stage delays the selected TAP signal to produce the OUTPUT signal. The programmable encoder encodes the input delay selection data to provide signals for controlling the multiplexer and for adjusting the delay of the delay adjustment stage. The manner in which the encoder encodes each separate delay selection data value is adjustable so that each of the N selectable delays can be separately calibrated.

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Masaharu Goto, James O. Barnes and Ronnie E. Owens, "CMOS Programmable Delay Vernier," Hewlett-Packard Journal, Oct. 1994, pp. 51-58.

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