Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Patent
1988-03-30
1992-01-21
Wieder, Kenneth A.
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
324679, 73718, 73724, G01R 2726, G01R 912
Patent
active
050830910
ABSTRACT:
A measurement circuit provides an output signal as a function of an input signal. The measurement circuit includes a charge generator which provides packets of charge as a function of the input signal to a measurement element. The measurement element measures the charge provided and provides a measurement signal as a function of the charge received. The measurement signal is coupled to a feedback circuit which couples to switches in the charge generator to control production of charge packets. The feedback circuit provides at least one output signal indicative of the quantity or number of charge packets provided.
REFERENCES:
patent: 3518536 (1970-06-01), Lee et al.
patent: 3564923 (1967-09-01), Nudd, Jr. et al.
patent: 3657926 (1972-04-01), Munson et al.
patent: 3731072 (1973-05-01), Johnston
patent: 3820095 (1974-06-01), Wojtasinski et al.
patent: 3869676 (1975-03-01), Harrison et al.
patent: 3883812 (1975-05-01), Harrison et al.
patent: 3896374 (1975-07-01), Delafon
patent: 3955070 (1976-05-01), Suzuki et al.
patent: 4001813 (1977-01-01), Kosakowski
patent: 4054833 (1977-10-01), Briefer
patent: 4057755 (1977-11-01), Piesche
patent: 4091683 (1978-05-01), Delatorre
patent: 4093915 (1978-06-01), Briefer
patent: 4129863 (1978-12-01), Gray et al.
patent: 4145619 (1979-03-01), Tseng
patent: 4149231 (1979-04-01), Bukosky et al.
patent: 4165483 (1979-08-01), Holdren et al.
patent: 4180860 (1979-12-01), Driscoll et al.
patent: 4187459 (1980-02-01), Wolfendale
patent: 4187460 (1980-02-01), Dauge et al.
patent: 4187718 (1980-02-01), Shibasaki
patent: 4193063 (1980-03-01), Hitt et al.
patent: 4200863 (1980-04-01), Hodges et al.
patent: 4232300 (1980-11-01), Wright et al.
patent: 4242665 (1980-12-01), Mate
patent: 4262542 (1981-04-01), Freund, Jr. et al.
patent: 4322775 (1982-03-01), Delatorre
patent: 4322977 (1982-04-01), Sell et al.
patent: 4370890 (1983-02-01), Frick
patent: 4381677 (1983-05-01), Rusch et al.
patent: 4386312 (1983-05-01), Briefer
patent: 4387601 (1983-06-01), Azegami
patent: 4392382 (1983-07-01), Myers
patent: 4398426 (1983-08-01), Park et al.
patent: 4399440 (1983-08-01), Douglas
patent: 4403297 (1983-09-01), Tivy
patent: 4420753 (1983-12-01), Meyer-Ebrecht
patent: 4434451 (1984-02-01), Delatorre
patent: 4459856 (1984-07-01), Ko et al.
patent: 4467655 (1984-08-01), Lee
patent: 4494183 (1985-01-01), Bayer et al.
patent: 4504921 (1985-03-01), Nasuta et al.
patent: 4535283 (1985-08-01), Rabinovich
patent: 4550295 (1985-10-01), Sasaki
patent: 4570490 (1986-02-01), Antonazzi
patent: 4574250 (1986-03-01), Senderowicz
patent: 4644798 (1987-02-01), Tamura et al.
patent: 4663168 (1986-12-01), Venema
patent: 4743836 (1988-05-01), Grzybowski et al.
Hauser, Max W. et al., "Circuit and Technology Considerations for MOS Delta-Sigma A/D Converters," 1986 IEEE International Symposium on Circuits and Systems, May 5-7, 1986 (San Jose, CA) pp. 1310-1315.
Robert J. et al., "A Low-Voltage High Resolution CMOS A/D Converter with Analog Compensation," CICC '86 Conference, May 12-15, 1986.
"The Voltage-To-Frequency A/D Converter," A/DVISOR, National Semiconductor Corporation, vol. 4, No. 1, Feb. 1984, pp. 7 and 8.
Williams, Jim, "Monolithic CMOS-Switch IC Suits Diverse Applications," EDN, Oct. 4, 1984, pp. 183-194.
Anderson, Tom and Bruce Trump, "Clocked v-f Converter Tightens Accuracy and Raises Stability," Electronic Design, Sep. 6, 1984, pp. 234-244.
"uA9706 Digital-To-Analog Converter Evaluation Demonstrator Board," Fairchild, 1979, pp. 2-17.
Andreiev, Nikita, "User Concern for Controller-To-Computer Link Delays Analog Signal Interface Phaseout," Control Engineering, vol. 29, No. 6, May 1982, pp. 82-85.
Deran, Charles, "A New Standard for Electronic D/P Transmitter Selection," Instrument Society of America, National Conference and Exhibit, Oct. 15, 1978, pp. 457-461.
Candy, James C., "A Use of Double Integration in Sigma Delta Modulation," IEEE Transactions on Communications, vol. Com-33, No. 3, Mar. 1985.
Rose, Craig D., "A New Way to Cut the Cost of A-to-D Converters," Electronics, pp. 42-44, Mar. 31, 1986.
Suarez, Ricardo E. et al., "All-MOS Charge Redistribution Analog-To-Digital Conversion Techniques-Part II," Reprinted from IEEE J. Solid-State Circuits, vol. SC-10, pp. 379-385, Dec. 1975.
Landsburg, George, "A Charge-Balancing Monolithic A/D Converter," Reprinted from IEEE J. Solid-State Circuits, vol. SC-12, pp. 662-673, Dec. 1977.
McCharles, Robert H. et al., "An Algorithmic Anolog-To-Digital Converter," Reprinted from IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 96-97, 1977.
Gregorian, Roubik et al., "Switched-Capacitor Circuit Design," IEEE, vol. 71, No. 8, Aug. 1983.
Williams, Jim, "Digitize Transducer Outputs Directly at the Source," EDN, Jan. 10, 1985, pp. 201-208.
IEEE Transactions on Industrial Electronics and Control Instrumentation, vol. IECI-22, No. 3, Aug. 1975, pp. 430-432.
Preliminary Product Specification, National Semiconductors, HPCl6140 Controller.
Frick Roger L.
Schulte John P.
Rosemount Inc.
Wieder Kenneth A.
LandOfFree
Charged balanced feedback measurement circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Charged balanced feedback measurement circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charged balanced feedback measurement circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-117424