Three-electrode MOS electron device

Details Three-electrode MOS electron device Three-electrode MOS electron device

1982-02-01

1985-04-09

James, Andrew J.

357 232, 357 236, 357 237, 357 2314, 357 14, 357 49, H01L 2714

Patent

active

045105162

ABSTRACT:
An electron device resembling a MOS capacitor with two opposed terminals, except that the central dielectric substance includes a centralsemiconductor layer connected to a third terminal. An information carrying signal traveling depthwise through the layers is controlled by the variation of the depletion layers that are formed depthwise opposite each other by the action of the top and bottom electrodes. This control action takes the form of modulation of displacement current in the central dielectric substance. Pulse edge biasing of the device can cause two opposed depletion layers to approach each other in the central semiconductor layer achieving punch-through. An inverter circuit, formed by a pair of these devices forms the basis for a logic family. A transmission line, an EAROM, and a single-cell static random access memory are integrated circuit applications of the device.

REFERENCES:
patent: 3384792 (1968-05-01), Kazan et al.
patent: 3602982 (1971-09-01), Kooi
patent: 3808472 (1974-04-01), Engeler

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