Error driven interrupt for polled MPU systems

Details Error driven interrupt for polled MPU systems Error driven interrupt for polled MPU systems

1976-02-05

1980-09-30

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 304

Patent

active

042259177

ABSTRACT:
A data processing system in which a central processor polls one or more peripheral devices to initiate a data transfer or to enable a data transfer. The system includes logic associated with a peripheral device or with an interface device for sensing the occurrence of data handling errors such as parity errors, carrier loss, clear to send loss, data overrun or underflow, and for interrupting the central processor upon such occurrence to avoid polling that peripheral device unnecessarily. A status signal is also generated to inform the processor of the nature of the interrupt, so as to distinguish from, for example, the interrupt of another device which is operative to communicate by means of such interrupt rather than by polling.

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