Source-coupled FET logic type output circuit

Details Source-coupled FET logic type output circuit Source-coupled FET logic type output circuit

1990-10-05

1992-01-21

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, H03K 19017, H03K 190175

Patent

active

050830465

ABSTRACT:
In a source-coupled FET logic type output circuit, the drain electrodes of first and second FETs are coupled through a level shift element and load elements to a high-voltage power source, the gate electrodes of the FETs are respectively connected to first and second input terminals, and the source electrodes of these transistors which are coupled together are coupled to a low-voltage power source by a first constant-current power source. Furthermore, between the high-voltage power source and the low-voltage power source, there are connected a third FET with its gate electrode coupled to the drain electrode of the first FET, level shift elements, a second constant-current power source, a fourth FET with its gate electrode coupled to the drain electrode of the second FET, a level shift element, a third constant-current power source, a fifth FET with its gate electrode coupled between the fourth FET and the level shift element, a sixth FET with its gate electrode coupled between the third level shift element and the second constant-current power source, and fifth level shift element. An output signal with the potential corresponding to that of a complementary signal is obtained at an output terminal expending from a connection point between the fifth and sixth FETs.

REFERENCES:
patent: 4093925 (1978-06-01), Yokoyama
patent: 4945258 (1990-07-01), Picard et al.
patent: 4958094 (1990-09-01), Ishii et al.
patent: 4992681 (1991-02-01), Urakawa et al.
Japanese Patent Abstract, vol. 12, No. 308 (E-647) [3155], Aug. 22, 1988; Japanese Patent Document No. 63-74215, Apr. 4, 1988, Mitsubishi Electric Corp.
Japanese Patent Abstract, vol. 13, No. 34 (E-708) [3382], Jan. 25, 1989; Japanese Patent Document No. 63-232711, Sep. 28, 1988, NEC Corporation.
IBM Technical Disclosure Bulletin, vol. 18, No. 11, Apr. 1976; E. Colao et al., "Totem-Pole Driver for High-Capacitance Loads".

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